The History Of Cleopatra VII

The History Of Cleopatra VII Cleopatra VII was the last person to rule Egypt as an Egyptian pharaoh. After her death Egypt became a Roman province. She was a member of the Ptolemaic dynasty (a royal family which ruled Egypt during the Hellinistic Period-323 BC to 146 BC) of Ancient Egypt. She is therefore considered to be a descendant of one of Alexander the Greats generals who had seized control over Egypt after Alexanders death. Cleopatra learned Egyptian unlike other Ptolemies who spoke Greece and refused Egyptian and represented herself as the reincarnation of an Egyptian Goddess. Cleopatra VII ruled originally with her father Ptolemy XII Auletes (commonly name as Auletes and who ruled Egypt from 80 to 58 BC) and later with her brothers, Ptolemy XIII and Ptolemy XIV. Later she became a sole ruler. As pharaoh, she kept good relations with Julius Caesar (Roman General who played a critical role in the transformation from Roman Republic to Roman Empire) that solidified her grip on the throne. After Caesars assassination in 44 BC, she aligned with Mark Antony in opposition to Caesars legal heir and she bore the twins Cleopatra Selene II and Alexander Helios, and another son, Ptolemy Philadelphus. Mark Antony was defeated by Octavian (the future emperor Augustus) and hence Egypt became the Roman province of Aegyptus. Though Cleopatra was an Egyptian pharaoh but she basically belonged to the Ptolemaic dynasty which was Hellenistic. Cleopatras mother language was Greek but still was the first ruler of the dynasty to learn Egyptian. She also adopted Egyptian beliefs and deities. Her patron deity was Isis (a Goddess in Ancient Egyptian religious beliefs) and thus was considered the re-incarnation and embodiment of the goddess. Her death marked the end of the Ptolemaic Kingdom and Hellenistic period and the beginning of the Roman era in the eastern Mediterranean. The above picture displays the bust of Cleopatra VII who is depicted as a great beauty and her legacy still survives in various works of art and dramas. William Shakespeares Antony and Cleopatra, Jules Massenets opera, Clà ©opà ¢tre are some examples of dramatizations inspired by Cleopatras life. REIGN 51 BC TO 12 August 30 BC SUCCESSOR None (Egypt was annexed by Rome) SPOUSE Ptolemy XIII Theos Philopator Ptolemy XIV Julius Caesar (not legally wed) Mark Antony FATHER Ptolemy XII Auletes MOTHER Cleopatra V of Egypt BORN 69 BC DIED 12th August 30 BC (aged 39) BURIAL Burial was done in Alexandria, Egypt Cleopatra in the Roman Civil War In the Roman civil war between the Caesarean party which was led by Mark Antony and Octavian and party led by Marcus Junius Brutus and Gaius Cassius Longinus who assassinated Julius Caesar. Cleopatra sided with the Caesarean party because of her past. Brutus and Cassius together and sailed to the East of the Roman Empire and conquered large areas and established their military bases. Now Cassius wanted to invade Egypt to seize the treasures of that country and to take the revenge from the queen as she refused his request to send him supplies punish the queen for her refusal of Cassius request to send him supplies and her support for Dolabella (a Roman General). At that time in Egypt there was famine and an epidemic which became an important reason why Cassius thought that Egypt could easily be conquered. But still he could not execute the invasion of Egypt because at the end of 43 BC Brutus called him back to Smyrna (an ancient city located at a central and strategic point on the Aegean coast of Anatolia now located in Turkey). Cassius tried to blockade Cleopatras way to the Caesareans. Nevertheless Cleopatra sailed with her military from Alexandria to the west along the Libyan coast to join the Caesarean leaders but she was forced to return to Egypt because her ships were damaged by a violent storm and she became ill. Relationship with Julius Caesar Cleopatra became Caesars mistress, and nine months after their first meeting, in 47 BC, Cleopatra gave birth to their son, Ptolemy Caesar, nicknamed Caesorian , which means little Caesar. At this point Caesar cancelled his plans to annex Egypt, instead backing Cleopatras claim to the throne. After a war lasting six months between the party of Ptolemy XIII and the Roman army of Caesar, Ptolemy XIII was drowned in the Nile (longest river of the world situated in Egypt) and Caesar restored Cleopatra to her throne and assigned her younger brother Ptolemy IV as her new co-rule. Although Cleopatra was 21 years old when they met and Caesar was 52, they became lovers during Caesars stay in Egypt between 48 BC and 47 BC. Cleopatra claimed Caesar was the father of her son and wanted his son to be the heir of Julius Caesar but instead of making his son caesorian, his heir, he chose his grandnephew Octavian. But Caesar even erected a golden statue of Cleopatra represented as Isis in the temple of Venus Genetrix (the mythical ancestress of Caesars family), which was situated at the Forum Julium (a forum built by Julius Caesar in Rome). Caesar was assassinated on 15 March, 44 BC. At that time Cleopatra was in Rome along with her outrages. After Caesars assassination Cleopatra returned to Egypt with her relatives. After the death of Ptolemy XIV who was allegedly poisoned by his elder sister, Cleopatra made her son Caesorian, her successor and gave her an epithet (an epithet as a descriptive word or phrase given to someone) Theos Philopator Philometor which means Father and mother loving God. Cleopatra and Mark Antony Coin of Antony and Cleopatra In 41 BC, Mark Antony, one of the triumvirs (name historians give to the official political alliance of Gaius Julius Caesar Octavians, later known as Augustus) who ruled Rome after the assassination of Julius Caesar. Dellius had to summon Cleopatra to Tarsus (a historical city in south eastern Turkey) to meet there Antony and answer questions about her loyalty. During the Roman civil war she allegedly paid much money to Cassius due to which Antony lost his trust on Dellius. Actually it seemed that in reality Antony wanted Cleopatras promise to support his war against the Parthians (citizens of Parthia a region of North eastern Iran). Cleopatra had Antony order the death of her sister Arsinoe to safeguard herself and her son, Caesarion. Arsinoe at that time was living at the temples of Artemis in Ephesus (Artemis is one of the religious Greek deities which is situated in Ephesus which is an ancient Greek city). On 25 December 40 BC, Cleopatra gave birth to twins fathered by Antony, Alexander Helios and Cleopatra Selene II. Four years later, Antony visited Alexandria again on route to make war with the Parthians. Donations of Alexandria was a religious-political statement by Cleopatra VII and Mark Antony in which they distributed lands of Rome and Parthia amongst Cleopatras children and granted them many titles especially for Caesarian who was the son of Julius Caesar. Donations of Alexandria was announced in late 34 BC, followed by Antonys conquest of Armenia (a client state of roman and Persian Empires stretching from Caspian to Mediterranean sea), Cleopatra and Caesarian were crowned co-rulers of Egypt and Cyprus. Cleopatra Selene II was crowned ruler of Cyrenaica and Libya and Ptolemy Philadelphus was crowned ruler of Phoenicia, Syria, and Cilicia. Donations of Alexandria were also a main reason for The Final war of the Roman Republic. Cleopatra was also given the title of Queen of Kings by Antonio. Her enemies in Rome feared that Cleopatra was planning a war of revenge that was between the whole of East against the Rome and establish herself as empress of the world at Rome and inaugurate a new universal kingdom. Caesarian was given co-regency with Cleopatra and was also given many titles such as god, son of god and king of kings. Egyptians thought Cleopatra to be a reincarnation of goddess Isis, as she called herself (NEA Isis). Relations between Antony and Octavian finally broke down in 33 BC, and Octavian declared a war against Egypt. In 31 BC Antonys forces faced the Romans in a naval action off the coast of Actium. Cleopatra was present with an army of her own. But Octavians invaded Egypt in the Battle of Actium and thus Antony and Cleopatra lost this war and thus the Roman Empire took over the Egypt. As he approached Alexandria, Antonys armies deserted to Octavian on August 1, 30 BC. DEATH This picture above shows the death of Cleopatra which was drawn by Guido Cagnacci in 1658. There have been many stories about the death of Cleopatra VII such as according to the ancient sources; particularly the Roman ones think that Cleopatra killed herself by inducing an Egyptian cobra to bite her. The oldest source is Strabo who was a Greek historian, geographer and a philosopher says that there are two stories: That she applied a toxic ointment OR That she was bitten by an asp. Other authors have questioned these historical accounts, stating that it is possible that Augustus had her killed. In 2010, the German historian Christophe Schaefer challenged all other theories, declaring that the queen had actually been poisoned and died from drinking a mixture of poisons. After studying historic texts and consulting with toxicologists, the historian concluded that the asp could not have caused a slow and pain free death, since the asp (Egyptian cobra) venom paralyses parts of the body, starting with the eyes, before causing death. Schaefer and his toxicologist Dietrich Mebs decided Cleopatra used a mixture of hemlock, wolfsbane and opium. Plutarch, writing about 130 years after the event has also mentioned the asp to be the major reason for Cleopatras death. He reports that Octavian succeeded in capturing Cleopatra in her Mausoleum after the death of Antony. He ordered his freedman Epaphroditus to guard her to prevent her from committing suicide because he allegedly wanted to present her in his triumph. But Cleopatra still was able to suicide by provoking the asp (cobra) to bite her on her arm. Suetonius, writing about the same time as Plutarch, also says Cleopatra died from an asp bite. Shakespeare also gave his own theory on the death of Cleopatra which gives us the image of Cleopatra clutching the snake to her breast. Before him, it was generally agreed that she was bitten on the arm. The site of their Mausoleum (a monument) is uncertain, though it is thought by the Egyptian Antiquities Service, to be in or near the temple of Taposiris Magna south west of Alexandria. Cleopatras son by Caesar, Caesarian, was proclaimed pharaoh by the Egyptians, after Alexandria fell to Octavian. Caesarean was captured and killed by Octavians. CONCLUSION: Why the women in world history were not given due importance? By taking the example of Cleopatra VII, the reasons why women were not given importance are: Cleopatra being the mother was more concerned about her children. She always tried her children to get throne unlike Julius Caesar who chose his grandnephew. Women are more directed towards their own children rather than caring about their kingdom. Cleopatra was not much concerned for her empire or the kingdom and was more aligned towards her family. Donations of Alexandria is the most important example which clearly explains that Cleopatra cared only about her family. She could have given those empires to some more educated or strong and a better person which could have helped her and Antony in the battle against Octavians. Well these were the main reasons why I think women were not given due importance in history.

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Unlike any other form of literature or entertainment, Fairy Tales help children to discover their identity and suggest experiences needed to develop their character. In Bruno Bettelheim’s â€Å"Life Divined from the Inside† Bettelheim states that â€Å"Fairy Tales intimate that a rewarding, good life is within one’s reach despite adversity-but only if one does not shy away from the hazardous struggles without which one can never achieve true identity (Bettelheim 106). Anne Sexton’s â€Å"Cinderella† is a perfect example of Bettelheim’s definition of a Fairy Tale.   Ã‚  Ã‚  Ã‚  Ã‚  The story of Cinderella is a classic story that has had many different versions. Anne Sexton’s version, begins as Cinderella’s mother is on her death bed. She is telling Cinderella to â€Å"Be Devout. Be Good. Then I will smile down from heaven in the seam of a cloud.† (Sexton 85) With the death of Cinderella’s mother, we get Bettelheim’s first example of a Fairy Tale; adversity for Cinderella. As the story goes on, Cinderella’s father marries another woman. She has two daughters, making a family of five. Cinderella’s father dies, leaving Cinderella’s stepmother in charge of Cinderella and the family. With the loss of her father, it’s seem that all Cinderella can face is adversity. Cinderella became her stepmother and stepsisters maid; but kept her chin up. She tried to lead a good life, but faced so much adversity with her family. They made her sleep on the sooty hearth every night; which made her loo k li...

Central Processing Unit and Memory Location

MICROPROCESSOR 8085 †¢ Reference Book: – Ramesh S. Goankar, â€Å"Microprocessor Architecture, Programming and Applications with 8085†, 5th Edition, Prentice Hall †¢ Week 1 – Basic Concept and Ideas about Microprocessor. †¢ Week 2 – Architecture of 8085 †¢ Week 3 – Addressing Modes and Instruction set of 8085 †¢ Week 4 – Interrupts of 8085 †¢ Week 5 onwards – Peripherals. Basic Concepts of Microprocessors †¢ Differences between: – Microcomputer – a computer with a microprocessor as its CPU. Includes memory, I/O etc. Microprocessor – silicon chip which includes ALU, register circuits & control circuits – Microcontroller – silicon chip which includes microprocessor, memory & I/O in a single package. What is a Microprocessor? †¢ The word comes from the combination micro and processor. – Processor means a device that processes whatever. In this context proces sor means a device that processes numbers, specifically binary numbers, 0’s and 1’s. †¢ To process means to manipulate. It is a general term that describes all manipulation. Again in this content, it means to perform certain operations on the numbers that depend on the microprocessor’s design.What about micro? †¢ Micro is a new addition. – In the late 1960’s, processors were built using discrete elements. †¢ These devices performed the required operation, but were too large and too slow. – In the early 1970’s the microchip was invented. All of the components that made up the processor were now placed on a single piece of silicon. The size became several thousand times smaller and the speed became several hundred times faster. The â€Å"Micro†Processor was born. Was there ever a â€Å"mini†processor? †¢ No. – It went directly from discrete elements to a single chip. However, omparing todayâ€⠄¢s microprocessors to the ones built in the early 1970’s you find an extreme increase in the amount of integration. †¢ So, What is a microprocessor? Definition of the Microprocessor The microprocessor is a programmable device that takes in numbers, performs on them arithmetic or logical operations according to the program stored in memory and then produces other numbers as a result. Definition (Contd. ) †¢ Lets expand each of the underlined words: – Programmable device: The microprocessor can perform different sets of operations on the data it receives depending on the sequence of instructions supplied in the given program.By changing the program, the microprocessor manipulates the data in different ways. – Instructions: Each microprocessor is designed to execute a specific group of operations. This group of operations is called an instruction set. This instruction set defines what the microprocessor can and cannot do. Definition (Contd. ) – Ta kes in: The data that the microprocessor manipulates must come from somewhere. †¢ It comes from what is called â€Å"input devices†. †¢ These are devices that bring data into the system from the outside world. †¢ These represent devices such as a keyboard, a mouse, switches, and the like.Definition (Contd. ) – Numbers: The microprocessor has a very narrow view on life. It only understands binary numbers. A binary digit is called a bit (which comes from binary digit). The microprocessor recognizes and processes a group of bits together. This group of bits is called a â€Å"word†. The number of bits in a Microprocessor’s word, is a measure of its â€Å"abilities†. Definition (Contd. ) – Words, Bytes, etc. †¢ The earliest microprocessor (the Intel 8088 and Motorola’s 6800) recognized 8-bit words. – They processed information 8-bits at a time. That’s why they are called â€Å"8-bit processors†.They can handle large numbers, but in order to process these numbers, they broke them into 8-bit pieces and processed each group of 8-bits separately. †¢ Later microprocessors (8086 and 68000) were designed with 16-bit words. – A group of 8-bits were referred to as a â€Å"half-word† or â€Å"byte†. – A group of 4 bits is called a â€Å"nibble†. – Also, 32 bit groups were given the name â€Å"long word†. †¢ Today, all processors manipulate at least 32 bits at a time and there exists microprocessors that can process 64, 80, 128 bits Definition (Contd. ) – Arithmetic and Logic Operations: Every microprocessor has arithmetic operations such as add and subtract as part of its instruction set. – Most microprocessors will have operations such as multiply and divide. – Some of the newer ones will have complex operations such as square root. †¢ In addition, microprocessors have logic operations as well. Such as AND, OR, XOR, shift left, shift right, etc. †¢ Again, the number and types of operations define the microprocessor’s instruction set and depends on the specific microprocessor. Definition (Contd. ) – Stored in memory : †¢ First, what is memory? – Memory is the location where information is kept while not in current use. Memory is a collection of storage devices. Usually, each storage device holds one bit. Also, in most kinds of memory, these storage devices are grouped into groups of 8. These 8 storage locations can only be accessed together. So, one can only read or write in terms of bytes to and form memory. – Memory is usually measured by the number of bytes it can hold. It is measured in Kilos, Megas and lately Gigas. A Kilo in computer language is 210 =1024. So, a KB (KiloByte) is 1024 bytes. Mega is 1024 Kilos and Giga is 1024 Mega. Definition (Contd. ) – Stored in memory: †¢ When a program is entered into a computer, it is st ored in memory.Then as the microprocessor starts to execute the instructions, it brings the instructions from memory one at a time. †¢ Memory is also used to hold the data. – The microprocessor reads (brings in) the data from memory when it needs it and writes (stores) the results into memory when it is done. Definition (Contd. ) – Produces: For the user to see the result of the execution of the program, the results must be presented in a human readable form. †¢ The results must be presented on an output device. †¢ This can be the monitor, a paper from the printer, a simple LED or many other forms. A Microprocessor-based systemFrom the above description, we can draw the following block diagram to represent a microprocessor-based system: Input Output Memory Inside The Microprocessor †¢ Internally, the microprocessor is made up of 3 main units. – The Arithmetic/Logic Unit (ALU) – The Control Unit. – An array of registers for holdi ng data while it is being manipulated. Organization of a microprocessorbased system †¢ Let’s expand the picture a bit. I/O Input / Output ALU Register Array System Bus Memory ROM RAM Control Memory †¢ Memory stores information such as instructions and data in binary format (0 and 1).It provides this information to the microprocessor whenever it is needed. †¢ Usually, there is a memory â€Å"sub-system† in a microprocessor-based system. This sub-system includes: – The registers inside the microprocessor – Read Only Memory (ROM) †¢ used to store information that does not change. – Random Access Memory (RAM) (also known as Read/Write Memory). †¢ used to store information supplied by the user. Such as programs and data. Memory Map and Addresses †¢ The memory map is a picture representation of the address range and shows where the different memory chips are located within the address range. 000 0000 EPROM 3FFF 4400 Address Range of EPROM Chip Address Range RAM 1 RAM 2 RAM 3 Address Range of 1st RAM Chip 5FFF 6000 Address Range of 2nd RAM Chip 8FFF 9000 A3FF A400 Address Range of 3rd RAM Chip RAM 4 F7FF FFFF Address Range of 4th RAM Chip Memory †¢ To execute a program: – the user enters its instructions in binary format into the memory. – The microprocessor then reads these instructions and whatever data is needed from memory, executes the instructions and places the results either in memory or produces it on an output device. The three cycle instruction execution model To execute a program, the microprocessor â€Å"reads† each instruction from memory, â€Å"interprets† it, then â€Å"executes† it. †¢ To use the right names for the cycles: – The microprocessor fetches each instruction, – decodes it, – Then executes it. †¢ This sequence is continued until all instructions are performed. Machine Language †¢ The number of bits tha t form the â€Å"word† of a microprocessor is fixed for that particular processor. – These bits define a maximum number of combinations. †¢ For example an 8-bit microprocessor can have at most 28 = 256 different combinations. However, in most microprocessors, not all of these combinations are used. – Certain patterns are chosen and assigned specific meanings. – Each of these patterns forms an instruction for the microprocessor. – The complete set of patterns makes up the microprocessor’s machine language. The 8085 Machine Language †¢ The 8085 (from Intel) is an 8-bit microprocessor. – The 8085 uses a total of 246 bit patterns to form its instruction set. – These 246 patterns represent only 74 instructions. †¢ The reason for the difference is that some (actually most) instructions have multiple different formats. Because it is very difficult to enter the bit patterns correctly, they are usually entered in hexadeci mal instead of binary. †¢ For example, the combination 0011 1100 which translates into â€Å"increment the number in the register called the accumulator†, is usually entered as 3C. Assembly Language †¢ Entering the instructions using hexadecimal is quite easier than entering the binary combinations. – However, it still is difficult to understand what a program written in hexadecimal does. – So, each company defines a symbolic code for the instructions. – These codes are called â€Å"mnemonics†. The mnemonic for each instruction is usually a group of letters that suggest the operation performed. Assembly Language †¢ Using the same example from before, – 00111100 translates to 3C in hexadecimal (OPCODE) – Its mnemonic is: â€Å"INR A†. – INR stands for â€Å"increment register† and A is short for accumulator. †¢ Another example is: 1000 0000, – Which translates to 80 in hexadecimal. â€⠀œ Its mnemonic is â€Å"ADD B†. – â€Å"Add register B to the accumulator and keep the result in the accumulator†. Assembly Language †¢ It is important to remember that a machine language and its associated assembly language are completely machine dependent. In other words, they are not transferable from one microprocessor to a different one. †¢ For example, Motorolla has an 8-bit microprocessor called the 6800. – The 8085 machine language is very different from that of the 6800. So is the assembly language. – A program written for the 8085 cannot be executed on the 6800 and vice versa. â€Å"Assembling† The Program †¢ How does assembly language get translated into machine language? – There are two ways: – 1st there is â€Å"hand assembly†. †¢ The programmer translates each assembly language instruction into its equivalent hexadecimal code (machine language).Then the hexadecimal code is entered into memory. – The other possibility is a program called an â€Å"assembler†, which does the translation automatically. 8085 Microprocessor Architecture †¢ †¢ †¢ †¢ †¢ †¢ 8-bit general purpose  µp Capable of addressing 64 k of memory Has 40 pins Requires +5 v power supply Can operate with 3 MHz clock 8085 upward compatible Pins Power Supply: +5 V Frequency Generator is connected to those pins Input/Output/ Memory Read Write Multiplexed Address Data Bus Address latch Enable Address Bus †¢ System Bus – wires connecting memory & I/O to microprocessor – Address Bus Unidirectional †¢ Identifying peripheral or memory location – Data Bus †¢ Bidirectional †¢ Transferring data – Control Bus †¢ Synchronization signals †¢ Timing signals †¢ Control signal Architecture of Intel 8085 Microprocessor Intel 8085 Microprocessor †¢ Microprocessor consists of: – – – – – Control unit: control microprocessor operations. ALU: performs data processing function. Registers: provide storage internal to CPU. Interrupts Internal data bus The ALU †¢ In addition to the arithmetic & logic circuits, the ALU includes the accumulator, which is part of every arithmetic & logic operation. Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer. †¢ Registers – General Purpose Registers †¢ B, C, D, E, H & L (8 bit registers) †¢ Can be used singly †¢ Or can be used as 16 bit register pairs – BC, DE, HL †¢ H & L can be used as a data pointer (holds memory address) – Special Purpose Registers †¢ Accumulator (8 bit register) – Store 8 bit data – Store the result of an operation – Store 8 bit data during I/O transfer Accumulator Flags B C D E H L Program Counter Stack Pointer Address 6 8 Data †¢ Flag Register – 8 bit register – shows the status of the microprocessor before/after an operation – S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) & CY (carry flag) D7 S D6 Z D5 X D4 AC D3 X D2 P D1 X D0 CY – Sign Flag †¢ Used for indicating the sign of the data in the accumulator †¢ The sign flag is set if negative (1 – negative) †¢ The sign flag is reset if positive (0 –positive) †¢ Zero Flag – Is set if result obtained after an operation is 0 – Is set following an increment or decrement operation of that register 10110011 + 01001101 ————–1 00000000 †¢ Carry Flag Is set if there is a carry or borrow from arithmetic operation 1011 0101 + 0110 1100 ————–Carry 1 0010 0001 1011 0101 – 1100 1100 ————–Borrow 1 1110 1001 †¢ Auxillary Carry Flag – Is set if there is a carry out of bit 3 †¢ Parity Flag – Is set if parity is even – Is cleared if parity is odd The Internal Architecture †¢ We have already discussed the general purpose registers, the Accumulator, and the flags. †¢ The Program Counter (PC) – This is a register that is used to control the sequencing of the execution of instructions. – This register always holds the address of the next instruction. Since it holds an address, it must be 16 bits wide. The Internal Architecture †¢ The Stack pointer – The stack pointer is also a 16-bit register that is used to point into memory. – The memory this register points to is a special area called the stack. – The stack is an area of memory used to hold data that will be retreived soon. – The stack is usually accessed in a Last In First Out (LIFO) fashion. Non Programmable Registers †¢ Instruction Register & Decoder – Inst ruction is stored in IR after fetched by processor – Decoder decodes instruction in IR Internal Clock generator – 3. 125 MHz internally – 6. 5 MHz externally The Address and Data Busses †¢ The address bus has 8 signal lines A8 – A15 which are unidirectional. †¢ The other 8 address bits are multiplexed (time shared) with the 8 data bits. – So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. †¢ During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. – In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes. Demultiplexing AD7-AD0 From the above description, it becomes obvious that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. – The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. – To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7– AD0 when it is carrying the address bits.We use the ALE signal to enable this latch. Demultiplexing AD7-AD0 8085 A15-A8 ALE AD7-AD0 Latch A7- A0 D7- D0 – Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bi-directional data lines. Demultiplexing the Bus AD7 – AD0 †¢ †¢ †¢ †¢ The high order address is placed on the address bus and hold for 3 clk periods, The low o rder address is lost after the first clk period, this address needs to be hold however we need to use latch The address AD7 – AD0 is connected as inputs to the latch 74LS373.The ALE signal is connected to the enable (G) pin of the latch and the OC – Output control – of the latch is grounded The Overall Picture †¢ Putting all of the concepts together, we get: A15- A10 Chip Selection Circuit 8085 A15-A8 ALE AD7-AD0 Latch CS A9- A0 A7- A0 1K Byte Memory Chip WR RD IO/M D7- D0 RD WR Introduction to 8085 Instructions The 8085 Instructions – Since the 8085 is an 8-bit device it can have up to 28 (256) instructions. †¢ However, the 8085 only uses 246 combinations that represent a total of 74 instructions. – Most of the instructions have more than one format. These instructions can be grouped into five different groups: †¢ †¢ †¢ †¢ †¢ Data Transfer Operations Arithmetic Operations Logic Operations Branch Operations Machin e Control Operations Instruction and Data Formats †¢ Each instruction has two parts. – The first part is the task or operation to be performed. †¢ This part is called the â€Å"opcode† (operation code). – The second part is the data to be operated on †¢ Called the â€Å"operand†. Data Transfer Operations – These operations simply COPY the data from the source to the destination. – MOV, MVI, LDA, and STA – They transfer: †¢ †¢ †¢ †¢ Data between registers.Data Byte to a register or memory location. Data between a memory location and a register. Data between an IO Device and the accumulator. – The data in the source is not changed. The LXI instruction †¢ The 8085 provides an instruction to place the 16-bit data into the register pair in one step. †¢ LXI Rp, (Load eXtended Immediate) – The instruction LXI B 4000H will place the 16-bit number 4000 into the register pair B, C. â₠¬ ¢ The upper two digits are placed in the 1st register of the pair and the lower two digits in the 2nd . B 40 00 C LXI B 40 00H The Memory â€Å"Register† Most of the instructions of the 8085 can use a memory location in place of a register. – The memory location will become the â€Å"memory† register M. †¢ MOV M B – copy the data from register B into a memory location. – Which memory location? †¢ The memory location is identified by the contents of the HL register pair. – The 16-bit contents of the HL register pair are treated as a 16-bit address and used to identify the memory location. Using the Other Register Pairs – There is also an instruction for moving data from memory to the accumulator without disturbing the contents of the H and L register. †¢ LDAX Rp (LoaD Accumulator eXtended) Copy the 8-bit contents of the memory location identified by the Rp register pair into the Accumulator. – This instruction o nly uses the BC or DE pair. – It does not accept the HL pair. Indirect Addressing Mode †¢ Using data in memory directly (without loading first into a Microprocessor’s register) is called Indirect Addressing. †¢ Indirect addressing uses the data in a register pair as a 16-bit address to identify the memory location being accessed. – The HL register pair is always used in conjunction with the memory register â€Å"M†. – The BC and DE register pairs can be used to load data into the Accumultor using indirect addressing.Arithmetic Operations – Addition (ADD, ADI): – Any 8-bit number. – The contents of a register. – The contents of a memory location. †¢ Can be added to the contents of the accumulator and the result is stored in the accumulator. – Subtraction (SUB, SUI): – Any 8-bit number – The contents of a register – The contents of a memory location †¢ Can be subtracted from the contents of the accumulator. The result is stored in the accumulator. Arithmetic Operations Related to Memory †¢ These instructions perform an arithmetic operation using the contents of a memory location while they are still in memory. ADD – SUB – INR M M M / DCR M †¢ Add the contents of M to the Accumulator †¢ Sub the contents of M from the Accumulator †¢ Increment/decrement the contents of the memory location in place. – All of these use the contents of the HL register pair to identify the memory location being used. Arithmetic Operations – Increment (INR) and Decrement (DCR): †¢ The 8-bit contents of any memory location or any register can be directly incremented or decremented by 1. †¢ No need to disturb the contents of the accumulator. Manipulating Addresses †¢ Now that we have a 16-bit address in a register pair, how do we manipulate it? It is possible to manipulate a 16-bit address stored in a register pair as one entity using some special instructions. †¢ INX Rp †¢ DCX Rp (Increment the 16-bit number in the register pair) (Decrement the 16-bit number in the register pair) – The register pair is incremented or decremented as one entity. No need to worry about a carry from the lower 8-bits to the upper. It is taken care of automatically. Logic Operations †¢ These instructions perform logic operations on the contents of the accumulator. – ANA, ANI, ORA, ORI, XRA and XRI †¢ Source: Accumulator and – An 8-bit number – The contents of a register – The contents of a memory location Destination: Accumulator ANA R/M ANI # ORA ORI XRA XRI R/M # R/M # AND Accumulator With Reg/Mem AND Accumulator With an 8-bit number OR Accumulator With Reg/Mem OR Accumulator With an 8-bit number XOR Accumulator With Reg/Mem XOR Accumulator With an 8-bit number Logic Operations – Complement: †¢ 1’s complement of the contents of the accumulato r. CMA No operand Additional Logic Operations †¢ Rotate – Rotate the contents of the accumulator one position to the left or right. – RLC – RAL – RRC – RAR Rotate the accumulator left. Bit 7 goes to bit 0 AND the Carry flag. Rotate the accumulator left through the carry.Bit 7 goes to the carry and carry goes to bit 0. Rotate the accumulator right. Bit 0 goes to bit 7 AND the Carry flag. Rotate the accumulator right through the carry. Bit 0 goes to the carry and carry goes to bit 7. RLC vs. RLA Carry Flag †¢ RLC 7 6 5 4 3 2 1 0 Accumulator Carry Flag †¢ RAL 7 6 5 4 3 2 1 0 Accumulator Logical Operations †¢ Compare †¢ Compare the contents of a register or memory location with the contents of the accumulator. – CMP R/M Compare the contents of the register or memory location to the contents of the accumulator. Compare the 8-bit number to the contents of the accumulator. CPI # †¢ The compare instruction sets the flag s (Z, Cy, and S). †¢ The compare is done using an internal subtraction that does not change the contents of the accumulator. A – (R / M / #) Branch Operations †¢ Two types: – Unconditional branch. †¢ Go to a new location no matter what. – Conditional branch. †¢ Go to a new location if the condition is true. Unconditional Branch – JMP Address †¢ Jump to the address specified (Go to). – CALL Address †¢ Jump to the address specified but treat it as a subroutine. – RET †¢ Return from a subroutine. – The addresses supplied to all branch operations must be 16-bits.Conditional Branch – Go to new location if a specified condition is met. †¢ JZ Address (Jump on Zero) – Go to address specified if the Zero flag is set. †¢ JNZ Address (Jump on NOT Zero) – Go to address specified if the Zero flag is not set. †¢ JC Address (Jump on Carry) – Go to the address specified if the Carry flag is set. †¢ JNC Address (Jump on No Carry) – Go to the address specified if the Carry flag is not set. †¢ JP †¢ JM Address (Jump on Plus) Address (Jump on Minus) – Go to the address specified if the Sign flag is not set – Go to the address specified if the Sign flag is set.Machine Control – HLT †¢ Stop executing the program. – NOP †¢ No operation †¢ Exactly as it says, do nothing. †¢ Usually used for delay or to replace instructions during debugging. Operand Types †¢ There are different ways for specifying the operand: – There may not be an operand (implied operand) †¢ CMA – The operand may be an 8-bit number (immediate data) †¢ ADI 4FH – The operand may be an internal register (register) †¢ SUB B – The operand may be a 16-bit address (memory address) †¢ LDA 4000H Instruction Size †¢ Depending on the operand type, the instruction may have diff erent sizes.It will occupy a different number of memory bytes. – Typically, all instructions occupy one byte only. – The exception is any instruction that contains immediate data or a memory address. †¢ Instructions that include immediate data use two bytes. – One for the opcode and the other for the 8-bit data. †¢ Instructions that include a memory address occupy three bytes. – One for the opcode, and the other two for the 16-bit address. Instruction with Immediate Date †¢ Operation: Load an 8-bit number into the accumulator. – MVI A, 32 †¢ Operation: MVI A †¢ Operand: The number 32 †¢ Binary Code: 0011 1110 3E 1st byte. 011 0010 32 2nd byte. Instruction with a Memory Address †¢ Operation: go to address 2085. – Instruction: JMP 2085 †¢ Opcode: JMP †¢ Operand: 2085 †¢ Binary code: 1100 0011 C3 1000 0101 85 0010 0000 20 1st byte. 2nd byte 3rd byte Addressing Modes †¢ The microprocessor ha s different ways of specifying the data for the instruction. These are called â€Å"addressing modes†. †¢ The 8085 has four addressing modes: – – – – Implied Immediate Direct Indirect CMA MVI B, 45 LDA 4000 LDAX B †¢ Load the accumulator with the contents of the memory location whose address is stored in the register pair BC). Data Formats In an 8-bit microprocessor, data can be represented in one of four formats: †¢ †¢ †¢ †¢ ASCII BCD Signed Integer Unsigned Integer. – It is important to recognize that the microprocessor deals with 0’s and 1’s. †¢ It deals with values as strings of bits. †¢ It is the job of the user to add a meaning to these strings. Data Formats †¢ Assume the accumulator contains the following value: 0100 0001. – There are four ways of reading this value: †¢ It is an unsigned integer expressed in binary, the equivalent decimal number would be 65. †¢ It is a number expressed in BCD (Binary Coded Decimal) format. That would make it, 41. It is an ASCII representation of a letter. That would make it the letter A. †¢ It is a string of 0’s and 1’s where the 0th and the 6th bits are set to 1 while all other bits are set to 0. ASCII stands for American Standard Code for Information Interchange. Counters & Time Delays Counters †¢ A loop counter is set up by loading a register with a certain value †¢ Then using the DCR (to decrement) and INR (to increment) the contents of the register are updated. †¢ A loop is set up with a conditional jump instruction that loops back or not depending on whether the count has reached the termination count.Counters †¢ The operation of a loop counter can be described using the following flowchart. Initialize Body of loop Update the count No Is this Final Count? Yes Sample ALP for implementing a loop Using DCR instruction MVI C, 15H LOOP DCR C JNZ LOOP Using a Regist er Pair as a Loop Counter †¢ Using a single register, one can repeat a loop for a maximum count of 255 times. †¢ It is possible to increase this count by using a register pair for the loop counter instead of the single register. – A minor problem arises in how to test for the final count since DCX and INX do not modify the flags. However, if the loop is looking for when the count becomes zero, we can use a small trick by ORing the two registers in the pair and then checking the zero flag. Using a Register Pair as a Loop Counter †¢ The following is an example of a loop set up with a register pair as the loop counter. LXI B, 1000H LOOP DCX B MOV A, C ORA B JNZ LOOP Delays †¢ It was shown in Chapter 2 that each instruction passes through different combinations of Fetch, Memory Read, and Memory Write cycles. †¢ Knowing the combinations of cycles, one can calculate how long such an instruction would require to complete. The table in Appendix F of the book contains a column with the title B/M/T. – B for Number of Bytes – M for Number of Machine Cycles – T for Number of T-State. Delays †¢ Knowing how many T-States an instruction requires, and keeping in mind that a T-State is one clock cycle long, we can calculate the time using the following formula: Delay = No. of T-States / Frequency †¢ For example a â€Å"MVI† instruction uses 7 T-States. Therefore, if the Microprocessor is running at 2 MHz, the instruction would require 3. 5  µSeconds to complete. Delay loops †¢ We can use a loop to produce a certain amount of time delay in a program. The following is an example of a delay loop: MVI C, FFH LOOP DCR C JNZ LOOP 7 T-States 4 T-States 10 T-States †¢ The first instruction initializes the loop counter and is executed only once requiring only 7 T-States. †¢ The following two instructions form a loop that requires 14 T-States to execute and is repeated 255 times until C becomes 0. Del ay Loops (Contd. ) †¢ We need to keep in mind though that in the last iteration of the loop, the JNZ instruction will fail and require only 7 T-States rather than the 10. †¢ Therefore, we must deduct 3 T-States from the total delay to get an accurate delay calculation. To calculate the delay, we use the following formula: Tdelay = TO + TL – Tdelay = total delay – TO = delay outside the loop – TL = delay of the loop †¢ TO is the sum of all delays outside the loop. Delay Loops (Contd. ) †¢ Using these formulas, we can calculate the time delay for the previous example: †¢ TO = 7 T-States – Delay of the MVI instruction †¢ TL = (14 X 255) – 3 = 3567 T-States – 14 T-States for the 2 instructions repeated 255 times (FF16 = 25510) reduced by the 3 T-States for the final JNZ. Using a Register Pair as a Loop Counter †¢ Using a single register, one can repeat a loop for a maximum count of 255 times. It is possible to increase this count by using a register pair for the loop counter instead of the single register. – A minor problem arises in how to test for the final count since DCX and INX do not modify the flags. – However, if the loop is looking for when the count becomes zero, we can use a small trick by ORing the two registers in the pair and then checking the zero flag. Using a Register Pair as a Loop Counter †¢ The following is an example of a delay loop set up with a register pair as the loop counter. LXI B, 1000H LOOP DCX B MOV A, C ORA B JNZ LOOP 10 T-States 6 T-States 4 T-States 4 T-States 10 T-StatesUsing a Register Pair as a Loop Counter †¢ Using the same formula from before, we can calculate: †¢ TO = 10 T-States – The delay for the LXI instruction †¢ TL = (24 X 4096) – 3 = 98301 T- States – 24 T-States for the 4 instructions in the loop repeated 4096 times (100016 = 409610) reduced by the 3 TStates for the JNZ in the last iterat ion. Nested Loops †¢ Nested loops can be easily setup in Assembly language by using two registers for the two loop counters and updating the right register in the right loop. – In the figure, the body of loop2 can be before or after loop1.Initialize loop 2 Body of loop 2 Initialize loop 1 Body of loop 1 Update the count1 No Is this Final Count? Yes Update the count 2 No Is this Final Count? Yes Nested Loops for Delay †¢ Instead (or in conjunction with) Register Pairs, a nested loop structure can be used to increase the total delay produced. MVI B, 10H LOOP2 MVI C, FFH LOOP1 DCR C JNZ LOOP1 DCR B JNZ LOOP2 7 T-States 7 T-States 4 T-States 10 T-States 4 T-States 10 T-States Delay Calculation of Nested Loops †¢ The calculation remains the same except that it the formula must be applied recursively to each loop. Start with the inner loop, then plug that delay in the calculation of the outer loop. †¢ Delay of inner loop – TO1 = 7 T-States †¢ MVI C, FFH instruction – TL1 = (255 X 14) – 3 = 3567 T-States †¢ 14 T-States for the DCR C and JNZ instructions repeated 255 Delay Calculation of Nested Loops †¢ Delay of outer loop – TO2 = 7 T-States †¢ MVI B, 10H instruction – TL1 = (16 X (14 + 3574)) – 3 = 57405 T-States †¢ 14 T-States for the DCR B and JNZ instructions and 3574 T-States for loop1 repeated 16 times (1016 = 1610) minus 3 for the final JNZ. – TDelay = 7 + 57405 = 57412 T-States †¢ Total Delay – TDelay = 57412 X 0. 5  µSec = 28. 06 mSec Increasing the delay †¢ The delay can be further increased by using register pairs for each of the loop counters in the nested loops setup. †¢ It can also be increased by adding dummy instructions (like NOP) in the body of the loop. Timing Diagram Representation of Various Control signals generated during Execution of an Instruction. Following Buses and Control Signals must be shown in a Timing Diagram: â € ¢Higher Order Address Bus. †¢Lower Address/Data bus †¢ALE †¢RD †¢WR †¢IO/M Timing Diagram Instruction: A000h MOV A,B Corresponding Coding: A000h 78 Timing Diagram Instruction: A000h MOV A,B Corresponding Coding: A000h 78OFC 8085 Memory Timing Diagram Instruction: A000h MOV A,B 00h T1 T2 T3 T4 A0h A15- A8 (Higher Order Address bus) Corresponding Coding: A000h 78 78h ALE RD OFC WR 8085 Memory IO/M Op-code fetch Cycle Timing Diagram Instruction: A000h MVI A,45h Corresponding Coding: A000h A001h 3E 45 Timing Diagram Instruction: A000h MVI A,45h OFC MEMR Corresponding Coding: A000h A001h 3E 45 8085 Memory Timing Diagram T1 T2 T3 T4 T5 T6 T7 A0h A0h A15- A8 (Higher Order Address bus) 00h 3Eh 01h 45h DA7-DA0 (Lower order address/data Bus) Instruction: A000h MVI A,45h Corresponding Coding: A000h A001h 3E 45 WR RD ALEIO/M Op-Code Fetch Cycle Memory Read Cycle Timing Diagram Instruction: A000h LXI A,FO45h Corresponding Coding: A000h A001h A002h 21 45 F0 Timing Dia gram Instruction: A000h LXI A,FO45h OFC MEMR MEMR Corresponding Coding: A000h A001h A002h 21 45 F0 8085 Memory Timing Diagram Op-Code Fetch Cycle Memory Read Cycle Memory Read Cycle T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 A0h A0h A0h A15- A8 (Higher Order Address bus) 00h 21h 01h 45h 02h F0h DA7-DA0 (Lower order address/data Bus) ALE RD WR IO/M Timing Diagram Instruction: A000h MOV A,M Corresponding Coding: A000h 7E Timing Diagram Instruction: A000h MOV A,MOFC MEMR Corresponding Coding: A000h 7E 8085 Memory Timing Diagram T1 T2 T3 T4 T5 T6 T7 A0h Content Of Reg H A15- A8 (Higher Order Address bus) Instruction: A000h MOV A,M Corresponding Coding: A000h 7E 00h 7Eh L Reg Content Of M DA7-DA0 (Lower order address/data Bus) ALE RD WR IO/M Op-Code Fetch Cycle Memory Read Cycle Timing Diagram Instruction: A000h MOV M,A Corresponding Coding: A000h 77 Timing Diagram Instruction: A000h MOV M,A OFC MEMW Corresponding Coding: A000h 77 8085 Memory Timing Diagram T1 T2 T3 T4 T5 T6 T7 A0h Content Of Reg H A15- A8 (Higher Order Address bus)Instruction: A000h MOV M,A Corresponding Coding: A000h 77 00h 7Eh L Reg Content of Reg A DA7-DA0 (Lower order address/data Bus) ALE RD WR IO/M Op-Code Fetch Cycle Memory Write Cycle Chapter 9 Stack and Subroutines The Stack †¢ The stack is an area of memory identified by the programmer for temporary storage of information. †¢ The stack is a LIFO structure. – Last In First Out. †¢ The stack normally grows backwards into memory. – In other words, the programmer defines the bottom of the stack and the stack grows up into reducing address range. The Stack grows backwards into memory Memory Bottom of the Stack The Stack Given that the stack grows backwards into memory, it is customary to place the bottom of the stack at the end of memory to keep it as far away from user programs as possible. †¢ In the 8085, the stack is defined by setting the SP (Stack Pointer) register. LXI SP, FFFFH †¢ This sets the Stack Pointer to location FFFFH (end of memory for the 8085). Saving Information on the Stack †¢ Information is saved on the stack by PUSHing it on. – It is retrieved from the stack by POPing it off. †¢ The 8085 provides two instructions: PUSH and POP for storing information on the stack and retrieving it back. – Both PUSH and POP work with register pairs ONLY.The PUSH Instruction †¢ PUSH B – Decrement SP – Copy the contents of register B to the memory location pointed to by SP – Decrement BSP C F3 12 – Copy the contents of register C to the memory location pointed to by SP F3 FFFB FFFC FFFD FFFE FFFF 12 SP The POP Instruction †¢ POP D – Copy the contents of the memory location pointed to by the SP to register E – Increment SP – Copy the contents of the memory location D E F3 12 pointed to by the SP to register D – Increment SP F3 SP FFFB FFFC FFFD FFFE FFFF 12 Operation of the Stack †¢ During pushing, the stack operates in a â€Å"decrement then store† style. The stack pointer is decremented first, then the information is placed on the stack. †¢ During poping, the stack operates in a â€Å"use then increment† style. – The information is retrieved from the top of the the stack and then the pointer is incremented. †¢ The SP pointer always points to â€Å"the top of the stack†. LIFO †¢ The order of PUSHs and POPs must be opposite of each other in order to retrieve information back into its original location. PUSH B PUSH D †¦ POP D POP B The PSW Register Pair †¢ The 8085 recognizes one additional register pair called the PSW (Program Status Word). This register pair is made up of the Accumulator and the Flags registers. †¢ It is possible to push the PSW onto the stack, do whatever operations are needed, then POP it off of the stack. – The result is that the contents of the Accumulator and the status of the Flags are ret urned to what they were before the operations were executed. Subroutines †¢ A subroutine is a group of instructions that will be used repeatedly in different locations of the program. – Rather than repeat the same instructions several times, they can be grouped into a subroutine that is called from the different locations. In Assembly language, a subroutine can exist anywhere in the code. – However, it is customary to place subroutines separately from the main program. Subroutines †¢ The 8085 has two instructions for dealing with subroutines. – The CALL instruction is used to redirect program execution to the subroutine. – The RTE insutruction is used to return the execution to the calling routine. The CALL Instruction †¢ CALL 4000H – Push the address of the instruction immediately following the CALL onto the stack 2000 CALL 4000 2003 counter – Load the program PC 2 0 0 3with the 16-bit address supplied with the CALL instructi on. FFFB FFFC FFFD FFFE FFFF 3 20 SP The RTE Instruction †¢ RTE – Retrieve the return address from the top of the stack – Load the program counter with the return address. 2003 PC 4014 4015 †¦ RTE FFFB FFFC FFFD FFFE FFFF 03 20 SP Cautions †¢ The CALL instruction places the return address at the two memory locations immediately before where the Stack Pointer is pointing. – You must set the SP correctly BEFORE using the CALL instruction. †¢ The RTE instruction takes the contents of the two memory locations at the top of the stack and uses these as the return address. – Do not modify the stack pointer in a subroutine. You will loose the return address.Passing Data to a Subroutine †¢ In Assembly Language data is passed to a subroutine through registers. – The data is stored in one of the registers by the calling program and the subroutine uses the value from the register. †¢ The other possibility is to use agreed upon mem ory locations. – The calling program stores the data in the memory location and the subroutine retrieves the data from the location and uses it. Call by Reference and Call by Value †¢ If the subroutine performs operations on the contents of the registers, then these modifications will be transferred back to the calling program upon returning from a subroutine. Call by reference †¢ If this is not desired, the subroutine should PUSH all the registers it needs on the stack on entry and POP them on return. – The original values are restored before execution returns to the calling program. Cautions with PUSH and POP †¢ PUSH and POP should be used in opposite order. †¢ There has to be as many POP’s as there are PUSH’s. – If not, the RET statement will pick up the wrong information from the top of the stack and the program will fail. †¢ It is not advisable to place PUSH or POP inside a loop. Conditional CALL and RTE Instructions à ¢â‚¬ ¢ The 8085 supports conditional CALL and conditional RTE instructions. The same conditions used with conditional JUMP instructions can be used. – – – – – CC, call subroutine if Carry flag is set. CNC, call subroutine if Carry flag is not set RC, return from subroutine if Carry flag is set RNC, return from subroutine if Carry flag is not set Etc. A Proper Subroutine †¢ According to Software Engineering practices, a proper subroutine: – Is only entered with a CALL and exited with an RTE – Has a single entry point †¢ Do not use a CALL statement to jump into different points of the same subroutine. – Has a single exit point †¢ There should be one return statement from any subroutine. Following these rules, there should not be any confusion with PUSH and POP usage. The Design and Operation of Memory Memory in a microprocessor system is where information (data and instructions) is kept. It can be classified into t wo main types: ? ? Main memory (RAM and ROM) Storage memory (Disks , CD ROMs, etc. ) The simple view of RAM is that it is made up of registers that are made up of flip-flops (or memory elements). ? ROM on the other hand uses diodes instead of the flip-flops to permanently hold the information. The number of flip-flops in a â€Å"memory register† determines the size of the memory word. Accessing Information in Memory For the microprocessor to access (Read or Write) information in memory (RAM or ROM), it needs to do the following: Select the right memory chip (using part of the address bus). Identify the memory location (using the rest of the address bus). Access the data (using the data bus). 2 Tri-State Buffers An important circuit element that is used extensively in memory. This buffer is a logic circuit that has three states: Logic 0, logic1, and high impedance. When this circuit is in high impedance mode it looks as if it is disconnected from the output completely.The Outp ut is Low The Output is High High Impedance 3 The Tri-State Buffer This circuit has two inputs and one output. The first input behaves like the normal input for the circuit. The second input is an â€Å"enable†. ? ? If it is set high, the output follows the proper circuit behavior. If it is set low, the output looks like a wire connected to nothing. Output Input OR Input Output Enable Enable 4 The Basic Memory Element The basic memory element is similar to a D latch. This latch has an input where the data comes in. It has an enable input and an output on which data comes out. Data Input D Data Output QEnable EN 5 The Basic Memory Element However, this is not safe. Data is always present on the input and the output is always set to the contents of the latch. To avoid this, tri-state buffers are added at the input and output of the latch. Data Input D Data Output Q RD Enable EN WR 6 The Basic Memory Element The WR signal controls the input buffer. The bar over WR means that thi s is an active low signal. So, if WR is 0 the input data reaches the latch input. If WR is 1 the input of the latch looks like a wire connected to nothing. The RD signal controls the output in a similar manner. A Memory â€Å"Register† If we take four of these latches and connect them together, we would have a 4-bit memory register I0 WR I1 I2 I3 D Q EN EN RD D Q EN D Q EN D Q EN O0 O1 O2 O3 8 A group of memory registers D0 o D1 o o D2 o D3 WR D EN Q D EN Q D EN Q D EN Q D Q D EN Q D EN Q D EN Q Expanding on this scheme to add more memory registers we get the diagram to the right. EN D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q o o o o RD D0 D1 D2 9 D3 Externally Initiated Operations External devices can initiate (start) one of the 4 following operations: Reset ?All operations are stopped and the program counter is reset to 0000. The microprocessor’s operations are interrupted and the microprocessor executes what is called a â€Å"service routine†. Th is routine â€Å"handles† the interrupt, (perform the necessary operations). Then the microprocessor returns to its previous operations and continues. Interrupt ? ? 10 A group of Memory Registers If we represent each memory location (Register) as a block we get the following I0 I1 I2 I3 WR EN0 EN1 EN2 EN3 RD O0 Input Buffers Memory Reg. 0 Memory Reg. 1 Memory Reg. 2 Memory Reg. 3 Output Buffers O1 O2 O3 11The Design of a Memory Chip Using the RD and WR controls we can determine the direction of flow either into or out of memory. Then using the appropriate Enable input we enable an individual memory register. What we have just designed is a memory with 4 locations and each location has 4 elements (bits). This memory would be called 4 X 4 [Number of location X number of bits per location]. 12 The Enable Inputs How do we produce these enable line? Since we can never have more than one of these enables active at the same time, we can have them encoded to reduce the number of line s coming into the chip.These encoded lines are the address lines for memory. 13 The Design of a Memory Chip So, the previous diagram would now look like the following: I I I I 0 1 2 3 WR A d d r e s s D e c o d e r Input Buffers Memory Reg. 0 Memory Reg. 1 Memory Reg. 2 Memory Reg. 3 Output Buffers A1 A0 RD O0 O1 O2 O3 14 The Design of a Memory Chip Since we have tri-state buffers on both the inputs and outputs of the flip flops, we can actually use one set of pins only. Input Buffers WR A1 A0 A D The chip Memory Reg. now look likeDthis: would 0 d e 0 D0 A1 A0 D1 D2 D3 d r e s s c o d e r Memory Reg. 1 Memory Reg. 2 Memory Reg. Output Buffers D1 D2 D3 RD RD WR 15 The steps of writing into Memory What happens when the programmer issues the STA instruction? The microprocessor would turn on the WR control (WR = 0) and turn off the RD control (RD = 1). The address is applied to the address decoder which generates a single Enable signal to turn on only one of the memory registers. The da ta is then applied on the data lines and it is stored into the enabled register. 16 Dimensions of Memory Memory is usually measured by two numbers: its length and its width (Length X Width). ? ? The length is the total number of locations.The width is the number of bits in each location. The length (total number of locations) is a function of the number of address lines. # of memory locations = 2( # of address lines) 210 = 1024 locations (1K) ? So, a memory chip with 10 address lines would have Looking at it from the other side, a memory chip with 4K locations would need ? Log2 4096=12 address lines 17 The 8085 and Memory The 8085 has 16 address lines. That means it can address 216 = 64K memory locations. Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc. ow would we use these address lines to control the multiple chips? 18 Chip Select Usually, each memory chip has a CS (Chip Select) input. The chip wil l only work if an active signal is applied on that input. To allow the use of multiple chips in the make up of memory, we need to use a number of the address lines for the purpose of â€Å"chip selection†. These address lines are decoded to generate the 2n necessary CS inputs for the memory chips to be used. 19 Chip Selection Example Assume that we need to build a memory system made up of 4 of the 4 X 4 memory chips we designed earlier.We will need to use 2 inputs and a decoder to identify which chip will be used at what time. The resulting design would now look like the one on the following slide. 20 Chip Selection Example RD WR D0 D1 RD WR A0 A1 CS RD WR A0 A1 CS RD WR A0 A1 CS RD WR A0 A1 CS A0 A1 A2 A3 2 X4 Decoder 21 Memory Map and Addresses The memory map is a picture representation of the address range and shows where the different memory chips are located within the address range. 0000 0000 EPROM 3FFF 4400 Address Range of EPROM Chip Address Range RAM 1 RAM 2 RAM 3 Ad dress Range of 1st RAM Chip 5FFF 6000 Address Range of 2nd RAM Chip FFF 9000 A3FF A400 Address Range of 3rd RAM Chip RAM 4 F7FF FFFF Address Range of 4th RAM Chip 22 Address Range of a Memory Chip The address range of a particular chip is the list of all addresses that are mapped to the chip. An example for the address range and its relationship to the memory chips would be the Post Office Boxes in the post office. †¢ Each box has its unique number that is assigned sequentially. (memory locations) †¢ The boxes are grouped into groups. (memory chips) †¢ The first box in a group has the number immediately after the last box in the previous group. 23 Address Range of a Memory ChipThe above example can be modified slightly to make it closer to our discussion on memory. †¢ Let’s say that this post office has only 1000 boxes. †¢ Let’s also say that these are grouped into 10 groups of 100 boxes each. Boxes 0000 to 0099 are in group 0, boxes 0100 to 01 99 are in group 1 and so on. We can look at the box number as if it is made up of two pieces: †¢ The group number and the box’s index within the group. †¢ So, box number 436 is the 36th box in the 4th group. The upper digit of the box number identifies the group and the lower two digits identify the box within the group. 24The 8085 and Address Ranges The 8085 has 16 address lines. So, it can address a total of 64K memory locations. If we use memory chips with 1K locations each, then we will need 64 such chips. The 1K memory chip needs 10 address lines to uniquely identify the 1K locations. (log21024 = 10) That leaves 6 address lines which is the exact number needed for selecting between the 64 different chips (log264 = 6). 25 The 8085 and Address Ranges Now, we can break up the 16-bit address of the 8085 into two pieces: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Chip Selection Location Selection within the ChipDepending on the combination on the address lines A15 – A10 , the address range of the specified chip is determined. 26 Chip Select Example A chip that uses the combination A15 – A10 = 001000 would have addresses that range from 2000H to 23FFH. Keep in mind that the 10 address lines on the chip gives a range of 00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips. The memory chip in this example would require the following circuit on its chip select input: A 10 A 11 A 12 A 13 A 14 A 15 CS 27 Chip Select Example If we change the above combination to the following: A 10 A 11 A 12 A 13 A 14 A 15 CSNow the chip would have addresses ranging from: 2400 to 27FF. Changing the combination of the address bits connected to the chip select changes the address range for the memory chip. 28 Chip Select Example To illustrate this with a picture: ? ? in the first case, the memory chip occupies the piece of the memory map identified as before. In the second case, it occupies the piece identified as after. Before Af ter 0000 2000 23FF 2400 27FF 0000 FFFF FFFF 29 High-Order vs. Low-Order Address Lines The address lines from a microprocessor can be classified into two types: High-Order ? Low-Order ?

The Effects Of Fetal Alcohol Syndrome Students - 1117 Words

their turn, playing with others and so for the, which can create a distance between them and their peers,† says Catterick (p. 114). By teaching students social cues in the classroom, you are better equipping them to make friends and not be isolated from their classmates because they are different or don’t fit in. Fetal Alcohol Syndrome students struggle with their memory and struggle to remember the things they are being taught. Teachers should implement a daily planner for the students in order to help them keep up with their assignments and help them remember what they are to do each day and night for school. According to Catterick, teachers should â€Å"ensure that learning is multisensory where possible to give the child the best chance of taking in the information† (p. 113) Fetal Alcohol Syndrome students are also more likely to be kinesthetic learners. Therefore, teachers should try and relay the needed information in more ways than just having the student take notes, or watch a video. Family Support Helping families in these situations are vital to helping their child succeed in life. Giving families resources can be the difference between doing nothing and early intervention. If a family suspects FAS in their child before the age of three, they are able to request an evaluation team to look into their situation. In order to do this, you can direct families to www.nofasorg and have them click on the resources table. This will lead them to the place where they canShow MoreRelated The Irreversible Damage Caused by Fetal Alcohol Syndrome Essay884 Words   |  4 Pagesher baby. Excessive exposure to alcohol during pregnancy can inflict serious, permanent physical and mental damage on her child. When a pregnant woman drinks alcohol she is making her child drink also. In knowing how Fetal Alcohol Syndrome can be prevented, what the symptoms are, and who and what make up the risk factors fetal alcohol syndrome can be better understood. The National Organization on Fetal Alcohol Syndrome states Fetal Alcohol Syndrome is the name given to a group of physicalRead MoreFetal Alcohol Syndrome And Its Effects1712 Words   |  7 Pages Fetal Alcohol Syndrome and its Effects On a Child’s Cognitive Development Dane D. Hrencher Kansas State University Fetal Alcohol Syndrome and its Effects On a Child’s Cognitive Development Alcohol is known as one the most dangerous teratogens. Every time a pregnant woman drinks, she allows alcohol to enter her blood stream and make its way into the placenta. Unlike the mother, the fetus is unable to break down alcohol that makes the blood alcohol level of the fetus the same orRead MoreFetal Alcohol Syndrome ( Fas )1404 Words   |  6 Pagesdisorders is Fetal Alcohol Syndrome (FAS). According to Feldman (2009), Fetal Alcohol Syndrome is a disorder that is induced by pregnant women who have consumed alcohol during the duration of their pregnancy, possibly resulting in mental deformity and delayed the growth of the child. Some characteristics of FAS include growth deficiency and central nervous system dysfunction (Mattson, 2006). Although the child may not be diagnosed with Fetal Alcohol Syndrome, if the child was exposed to alcohol duringRead MoreFetal Alcohol Syndrome Essay1727 Words   |  7 PagesFetal Alcohol Syndrome Fetal Alcohol Syndrome is an increasing problem in our world today. At least 5,000 infants are born each year with FAS, or about one out of every 750 live births, which is an alarming number. In the United States there has been a significant increase in the rate of infants born with FAS form 1 per 10,000 births in 1979 to 6.7 per 10,000 in 1993 (Chang, Wilikins-Haug, Berman, Goetz 1). In a report, Substance Abuse and the American Woman, sent out by the Center on AddictionRead MoreFetal Alcohol Spectrum Disorder ( Fasd )1603 Words   |  7 PagesFetal Alcohol Spectrum Disorder â€Å"Fetal Alcohol Spectrum Disorder (FASD) is an umbrella term describing the range of effects that can occur in an individual whose mother drank alcohol during pregnancy. These effects may include physical, mental, behavioral, and/or learning disabilities with possible lifelong implications† (HHS, 2005). FASD refers to conditions such as: fetal alcohol syndrome including partial FAS, fetal alcohol effects (FAE), alcohol related neurodevelopment disorder, alcohol-relatedRead MoreFetal Alcohol Syndrome1466 Words   |  6 PagesFetal Alcohol Syndrome â€Å"If women didn’t drink anymore during pregnancy, there would never be another baby born with Fetal Alcohol Syndrome or Fetal Alcohol Effect† (McCuen 33). This is a very powerful statement. It is also a very simple cure for an alarmingly high birth defect that all women have the power to stop. â€Å"Every year more than 40,000 American children are born with defects because their mother drank alcohol while pregnant â€Å" (McCuen 34). That is 1 to 3 per 1,000 live birthsRead MoreThe Effects Of Prenatal Alcohol Exposure On Children1388 Words   |  6 PagesThe Effects of Prenatal Alcohol Exposure On average, one in thirteen pregnant women have admitted to consuming one or more alcoholic beverage in their previous thirty days of pregnancy (â€Å"Fetal Alcohol Spectrum Disorders†). Though one drink may seem miniscule in the scope of an eight to nine month pregnancy, any amount of alcohol exposure can be detrimental to a developing child, leading to life-changing disorders such as fetal alcohol syndrome (FAS). Fetal alcohol syndrome, a severe potential consequenceRead MoreFetal Alcohol Syndrome FAS Essay2732 Words   |  11 PagesCould you ever imagine feeding your infant alcohol through a bottle? This is equivalent to what alcohol does to the fetus in the womb. This results in a tragic disease known as Fetal Alcohol Syndrome. Alcohol can affect a human body in many different ways. Alcohol can be the highlight of a party and make anything exciting, but also can seriously alter human life. It’s quite often that we see on the news another victim dead, or in critic al condition because their signs and symptoms were loud enoughRead MoreMarisa Leathers. Kathleen Mccoy. Development Of The Exceptional1537 Words   |  7 Pages Marisa Leathers Kathleen McCoy Development of the Exceptional Child April 16, 2017 Fetal Alcohol Spectrum Disorders Discovered in 1973, fetal alcohol spectrum disorders were recognized from a specific pattern of cardiac, craniofacial, and limb defects between unrelated infants. The one thing the infants all had in common was that they were all born to alcoholic mothers (Bradshaw). Fetal alcohol spectrum disorder, also referred to as FASD for short, can lead to numerous physical and mental defectsRead MorePrenatal Alcohol Exposure And Ability, Academic Achievement, And School Functioning Essay1238 Words   |  5 PagesIn the study titled Prenatal Alcohol Exposure and Ability, Academic Achievement, and School Functioning in Adolescence: A Longitudinal Follow- Up, there is a study conducted in order to show the correlation of academic problems to prenatal alcohol exposure, in which some of the children in the study had fetal alcohol syndrome and others did not. The main theory is that â€Å"Prenatal exposure to alcohol is associated with fetal alcohol syndrome (FAS) as well as other alcohol- related neurodevelopmental